Advanced VLSI Technique for Error Detection and Correction in Space Systems

Suresh TechLabs

This study introduces a novel approach to error detection and correction within Very Large-Scale Integration (VLSI) systems, specifically tailored for space applications. The core of this research is the development and implementation of a sophisticated 2-dimensional error correction code designed to significantly enhance memory reliability in the harsh conditions of outer space. Traditional error correction methods, while effective to a certain extent, fall short in addressing the complex phenomenon of burst errors—errors that occur in multiple bits simultaneously as a result of a single disruptive event, such as cosmic radiation. The proposed error correction scheme innovatively employs extended XOR operations, covering larger blocks of data, thus offering a more comprehensive solution for detecting and correcting burst errors. Moreover, the integration of Cyclic Redundancy Check (CRC) techniques further bolsters the error detection and correction capabilities of the system. Through a detailed comparison with existing methods, our study demonstrates that the proposed 2-dimensional code not only addresses the limitations of current error correction techniques but also contributes to the advancement of memory system reliability in space engineering. The implementation of this method is poised to provide better performance in environments where burst errors are prevalent, marking a significant step forward in the domain of space system design and reliability. 

 Key words: Error detection, Error correction, Cyclic Redundancy Check (CRC), XOR operations, burst errors, Space engineering, VLSI systems.  

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Design and Implementation of Trigonometric Functions with High Speed CORDIC Algorithm

Suresh TechLabs

The Present work focuses on realization of the exponential and converse exponential functions by utilizing the CORDIC algorithm. The exponential function finds its application in the areas of signal processing, image processing and video processing. The realization of the exponential functions forms the bottleneck for refining the performance of the design in terms of area and delay. The range of the inputs are extended from -7 to 7. The inputs are scaled by 65536 to improve the accuracy of the result. The output values are 1 floating point values and hence they are scaled by the 65536 to get the actual values. The exponential function was realized using the CORDIC algorithm in which addition/subtraction and shift operations were involved and hence the performance can be improved. The throughput of the model was enhanced by the utilizing the pipelining of the design. The algorithm has been realized using vhdl in the stratix II FPGA and the algorithm was synthesized using the Quartus -11 9.1 SP2 software.

 Keywords: Pipelined, Parallel,CORDIC, arcsine, arccosine, sine, cosine, FPGA, ASIC

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Router in Bi-Network on Chip with an Advanced FIFO Structure

Suresh TechLabs

Network on chip (NoC) becomes a promising solution for intercommunication infrastructure in System on Chip (SoC) as traditional methods exhibit severe bottlenecks at intercommunication among processor elements. However, designing of NoC is majorly complex because of lot of issues raise in terms of performance metrics such as system scalability, latency, power consumption and signal integrity. This paper discussed issues of memory unit in router and thereafter, proposing advanced memory structure. To obtain efficient data transfer, FIFO buffers are implemented in distributed RAM and virtual channels for FPGA based NoC. An advanced FIFO based memory units are proposed in NoC router and the performance is evaluated in Bi-directional NoC (Bi-NoC). The major motivation of this paper is to reduce burden of router while improving FIFO internal structure. To enhance the speed data transfer, Bi-NoC with a self-configurable intercommunication channel is proposed. The Simulations and synthesis results are proven guaranteed throughput, predictable latency, and fair network access highly provided when compared to recent works. Keywords: Network on Chip , system on chip , FIFO , FPGA.

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Project code on Design and Implementation of RISC Processor

Suresh TechLabs

This paper presents an efficient FPGA based low power pipelined 32-bit RISC processor with Floating Point Unit. RISC is a design philosophy where it reduces the complexity of the instruction set, which will reduce the amount of space, time, cost, power and heat etc.,. This processor is developed especially for Arithmetic operations of both fixed and floating point as it is implemented using dynamic branch prediction. This will increase flow in instruction pipeline and high effective performance. In RTL coding one can reduce the dynamic power by using clock gating technique. In this paper also implement Double Precision floating point arithmetic operations like addition, subtraction, multiplication and division. This architecture has become indispensable and increasingly important in many applications like signal processing, graphics and medical by using floating point operations. The necessary code is written in the hardware description language Verilog HDL. Quartus II 10.1 suite is used for software development, Modelsim is used for simulations and the design is implemented on Altera's Cyclone DElIFPGA.

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Advanced VLSI Technique for Error Detection and Correction in Space Systems - IJISEA Journal

This study introduces a novel approach to error detection and correction within Very Large-Scale Integration (VLSI) systems, specifically tailored for space applications. The core of this research is the development and implementation of a sophisticated 2-dimensional error correction code designed to significantly enhance memory reliability in the harsh conditions of outer space. Traditional error correction methods, while effective to a certain extent, fall short in addressing the complex phenomenon of burst errors—errors that occur in multiple bits simultaneously as a result of a single disruptive event, such as cosmic radiation. The proposed error correction scheme innovatively employs extended XOR operations, covering larger blocks of data, thus offering a more comprehensive solution for detecting and correcting burst errors. Moreover, the integration of Cyclic Redundancy Check (CRC) techniques further bolsters the error detection and correction capabilities of the system. Through a detailed comparison with existing methods, our study demonstrates that the proposed 2-dimensional code not only addresses the limitations of current error correction techniques but also contributes to the advancement of memory system reliability in space engineering. The implementation of this method is poised to provide better performance in environments where burst errors are prevalent, marking a significant step forward in the domain of space system design and reliability.

 

Key words: Error detection, Error correction, Cyclic Redundancy Check (CRC), XOR operations, burst errors, Space engineering, VLSI systems. 

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A Systematic Literature Review on Human Activity Recognition - Journal of Electrical Systems

https://journal.esrgroups.org/jes/article/view/2848 

Abstract

Human Activity Recognition (HAR) plays a significant role in several fields by automatically identifying and monitoring human activities using advanced techniques. It enhances safety, improves healthcare services, optimizes fitness routines, and enables context-aware applications in various fields. HAR contributes to a more efficient and intelligent interaction between humans and technology. It has emerged as an essential research domain with applications in healthcare, smart environments, and human-computer interaction. This study aims to provide a comprehensive survey of the evolving landscape of HAR, including key methodologies, techniques, and trends in existing research. The study discusses various applications of HAR and their significance in modern smart environments. The survey also highlights different types of HAR and data collection techniques. Additionally, it explores various methods for analyzing the collected data and provides a comprehensive analysis of existing human activity classification datasets. It offers valuable insights into understanding the strengths and limitations of various HAR techniques. The study also discusses various challenges and future directions for HAR.    

Suresh TechLabs

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Multimodal medical image fusion using residual network 50 in non subsampled contourlet transform - indexed in SCI

K. Koteswara Rao & K. Veera Swamy

To cite this article: K. Koteswara Rao & K. Veera Swamy (2023): Multimodal medical image

fusion using residual network 50 in non subsampled contourlet transform, The Imaging

Science Journal, DOI: 10.1080/13682199.2023.2175426

To link to this article: https://doi.org/10.1080/13682199.2023.2175426

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Coal Safety and Security System for monitoring the Environment with Driver less vehicle

The safety of coal mine is an important link in coal mine production, Gas disaster is the most harmful for the safety of coal mine production. During the process of mine development, it is very important to measure the gas, temperature and fire concentration in mines to safe the human life. Based on continuous revolution of coal mining technology, to forward this project about safety monitoring system of coal mine using Bluetooth technology. A system is designed using group of sensors which monitors the different environmental condition in underground mines and if value exceeds from threshold value, then the Miners are informed through buzzer. Another module is 16*2 LCD displays which is used to show the results of sensor condition in project. The system is flexible in the architecture of software and hardware, and can easily extend to other mine safety production fields. Keywords: Sensors, Bluetooth Technology, coal mine, underground mines

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Design and Implementation of 32-bit ALU with 32 Operations for FPGA-Based RISC Architecture Applications

The project focuses on the design and the implantation of a 32-bit Arithmetic Logic Unit (ALU) capable of performing 32 different arithmetic and logic operations based on select lines. The ALU is implemented using Verilog hardware description language (HDL) and synthesized on FPGA hardware. Each operation is selected using a 5-bit control input, enabling a wide range of arithmetic and logical computations. Primary objective is to showcase the ALU’s functionality and versatility across diverse computing tasks. To optimize power consumption and hardware utilization, the design incorporates clock gating techniques and pipelining, ensuring efficient operation in resource constrained environments. Pipelining enhances throughput by breakdown operations into sequential stages, maximizing alu utilization. Through extensive simulation and synthesis, the ALU design is rigorously validated demonstrating both correctness and efficiency in operation. Vivado was utilized for a synthesis and implementation process, ensuring compatibility with FPGA hardware. The ALU is synthesized on Artix 7. FPGA platform, containing 61 cells, 135 i/o port and 1005 nets. Its design to carry out various arithmetic and logic tasks with each operation chosen using a 5-bit control input. 

https://ijisea.org/Papers/V5S1/Design%20and%20Implementation%20of%2032-bit%20ALU%20with%2032%20Operations%20for%20FPGA-Based%20RISC%20Architecture%20Applications.pdf  

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Enhancing Scalability and Privacy in 5G-Enabled IoT Networks through Block chain Integration and AI Solutions - Indexed in Google Scholar : IJISEA

The proliferation of Internet of Things (IoT) devices in the digital landscape has ushered in a new era of connectivity, empowering billions of devices to communicate over the internet. However, the reliance on centralized protocols for data transfer poses significant security challenges. The emergence of 5G technology promises high-speed data transfer, yet it also underscores the need for robust security measures. Integrating Artificial Intelligence (AI) with 5G networks offers solutions to various challenges, including security concerns and the demand for autonomous systems like self-driving vehicles and virtual reality applications. Blockchain technology, known for its decentralized ledger system, presents an opportunity to address security and trust issues in IoT environments. However, integrating blockchain with IoT networks presents its own set of challenges, particularly in terms of throughput limitations. This paper addresses these challenges by proposing a solution that combines a Blockchain Distributed Network with the Raft consensus algorithm to enhance network scalability and throughput. Additionally, privacy concerns inherent in blockchain ledgers are addressed using zkLedger, a zero-knowledge based cryptographic solution. Through these innovations, this research contributes to the development of secure, scalable, and privacy-preserving 5G-enabled IoT networks.

 Key words: Blockchain, Artificial Intelligence, Internet of Things, 5G Network, Scalability, Privacy. Abbreviations: Blockchain (BC), Artificial Intelligence (AI), Internet of Things (IoT), 5G Network, Scalability (SC), Privacy (PR).

Suresh TechLabs

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Journal of Electrical System : SCI-mago Published

Abstract: - Unmanned Aerial Vehicles (UAVs) have grown into a more powerful type of data transmission due to this rapid progress of evolution of wireless communication technology. In addition, UAVs have been proven to be effective in a variety of applications, including intelligent transport, disaster risk management, surveillance, and environmental monitoring. When UAVs are deployed randomly, however, they can effectively accomplish challenging tasks because of the UAVs’ has low battery capacity, quick mobility, and dynamic in nature orientation. Due to this reason, a new technique must be designed for an optimal energy efficient UAV clustering as well as data routing protocols. In this work proposes a new hybrid model of Emperor penguin-based Generalized Approximate Reasoning Based Intelligent Control (EP-GARIC) cluster-based network topology. Furthermore, the optimal routing function is achieved by the proposed Artificial Jellyfish Optimization (AJO). The implementation of this research is carried out using Network Simulator (NS2). The simulation results displays the effective performance of the suggested approach in terms of reduced energy consumption, improved packet delivery ratio, reduced loss, and so on over compared to the conventional approaches. 

 Keywords: Clustering, Neural Network, Fuzzy method, Energy Efficiency, Parameter Tuning.

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https://link.springer.com/article/10.1007/s11042-023-16808-6

Recurrent neural network with emperor penguin-based Salp swarm (RNN- EPS²) algorithm for emoji based sentiment analysis

The opinions of the users are analyzed by the sentiment analysis process. Sometimes, the users reviewed their opinions using emojis and it is necessary to analyze them to find the classes (positive, negative, or neutral). However, the existing works lack the ability of emoji analysis in large databases, which induces computational complexity and reduces performance. To tackle those issues, we propose a novel Recurrent Neural network (RNN) with an Emperor Penguin-based Salp Swarm algorithm (EPS²) approach. The optimization algorithm can be used to choose the parameters of the RNN and provide better results. The experiments are conducted by taking the data from four social media platforms known as Reddit, Twitter, IMDB movie review, and Yelp dataset. The performance is analyzed by different metrics and compared the outcomes with other state-of-art works. From the results, it is found that our proposed approach effectively analyses the emojis from the social media platform and provides better results.

• Published: 28 September 2023

• (2023)
• Cite this article

Suresh TechLabs

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Published SCOPUS indexed Journal

Abstract—Unmanned Aerial Vehicles (UAVs) have evolved into a potent form of data transmission, benefiting from the rapid advancements in wireless communication technology. Furthermore, UAVs have demonstrated their effectiveness across diverse applications, such as intelligent transportation, disaster risk management, surveillance, and environmental monitoring. When UAVs are deployed randomly, however, they can effectively accomplish challenging tasks because of the UAVs’ has low battery capacity, quick mobility, and dynamic in nature orientation. Due to this reason, a new technique must be designed for an optimal energy efficient UAV clustering as well as data routing protocols. In this work proposes a new hybrid model of Emperor penguin-based Generalized Approximate Reasoning Based Intelligent Control (EP-GARIC) cluster-based network topology. Moreover, the proposed model achieves the most efficient routing function through the utilization of the novel Artificial Jellyfish Optimization (AJO) technique. The execution of this study is conducted within the Network Simulator (NS2) environment. The outcomes of the simulations distinctly demonstrate the notable effectiveness of the suggested methodology. This is evidenced by a marked decrease in energy consumption, a substantial improvement in packet delivery ratio, a noteworthy reduction in losses, and other comparable metrics when contrasted with established conventional methods. Keywords—Clustering, Neural Network, Fuzzy method, Energy Efficiency, Parameter Tuning.

Download Link : https://drive.google.com/file/d/18XCdJ7T6ijGfEdi4j5Py6tKJ2q4_mQ2D/view?usp=sharing

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Reducing Plagiarism from 67% to 3% - Engineering Journal

Plagiarism means using someone else’s work without giving them proper credit. In academic writing, plagiarizing involves using words, ideas, or information from a source without citing it correctly. In practice, this can mean a few different things.

Suresh TechLabs

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ACTA GEOPHYSICA - Publisher SPRINGER

Tropical cyclone detection in South Pacific and Atlantic coastal area using optical flow estimation and RESNET deep learning model

Tropical cyclones (TC) are among the worst natural disasters, that cause massive damage to property and lives. The meteorologists track these natural phenomena using Satellite imagery. The spiral rain bands appear in a cyclic pattern with an eye as a center in the satellite image. Automatic identification of the cyclic pattern is a challenging task due to the clouds present around the structure. Conventional approaches use only image data to detect the cyclic structure using deep learning algorithms. The training and testing data consist of positive and negative samples of TC. But the cyclic structure's texture pattern makes it difficult for the deep learning algorithms to extract useful features. This paper presents an automatic TC detection algorithm using optical flow estimation and deep learning algorithms to overcome this draw-back. The optical flow vectors are estimated using the Horn-Schunck estimator, the Liu-Shen estimator, and the Lagrange multiplier. The deep learning algorithms take the optical flow vectors as input during the training stage and extract the features to identify the cyclone's circular pattern. The software used for experimental analysis is MATLAB 2021a. The proposed method increases the accuracy of detecting the cyclone pattern through optical flow vectors compared to using the pixel intensity values. By using proposed method 98% of accuracy will be achieved when compared with the existing methods.

Author Keywords

Tropical cycloneConventional approachesDeep learning algorithmHorn-schunk estimatorLiu-shen estimatorThe Lagrange multiplier

Keywords Plus

RISK

Tropical cyclone detection in South Pacific and Atlantic coastal area using optical flow estimation and RESNET deep learning model-Web of Science Core Collection

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