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Design and comparative analysis of low power,area efficient optimized 10T Hybridfull adder for high performance Arithmetic and Logic Unit

Abstract

In this time of rapid invention and utilisation of battery-operated products, battery life is a

significant problem. Because the traditional Full Adder(FA) uses more energy, we used low power

FA circuitry in this study and examined how it functions in lieu of the traditional Full Adder

circuitry. Contrary to the latest State of Art, only ten transistors make up the suggested design,

which runs on a 0.8 supply voltage. This study compares and contrasts the present design with the

FA's suggested work in respect of power and delay. This design consumes low power of only

674.38 nWand is area efficient as it consists of only ten transistors. The presented design of FA

consumes less power and offers very less delay of only 2.3 ps than existing designs. TANNER EDA

is used to simulate proposed FA and using a 65nm CMOS technology.

Keyword:Addition, XOR, XNOR cell, Low power, Full adder (FA) Hybrid design.

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