The project focuses on the design and the implantation of a 32-bit Arithmetic Logic Unit (ALU)
capable of performing 32 different arithmetic and logic operations based on select lines. The ALU
is implemented using Verilog hardware description language (HDL) and synthesized on FPGA
hardware. Each operation is selected using a 5-bit control input, enabling a wide range of
arithmetic and logical computations. Primary objective is to showcase the ALU’s functionality and
versatility across diverse computing tasks. To optimize power consumption and hardware
utilization, the design incorporates clock gating techniques and pipelining, ensuring efficient
operation in resource constrained environments. Pipelining enhances throughput by breakdown
operations into sequential stages, maximizing alu utilization. Through extensive simulation and
synthesis, the ALU design is rigorously validated demonstrating both correctness and efficiency in
operation. Vivado was utilized for a synthesis and implementation process, ensuring compatibility
with FPGA hardware. The ALU is synthesized on Artix 7. FPGA platform, containing 61 cells, 135 i/o
port and 1005 nets. Its design to carry out various arithmetic and logic tasks with each operation
chosen using a 5-bit control input.