The Present work focuses on realization of the exponential and converse exponential functions by utilizing the CORDIC algorithm. The exponential function finds its application in the areas of signal processing, image processing and video processing. The realization of the exponential functions forms the bottleneck for refining the performance of the design in terms of area and delay. The range of the inputs are extended from -7 to 7. The inputs are scaled by 65536 to improve the accuracy of the result. The output values are 1 floating point values and hence they are scaled by the 65536 to get the actual values. The exponential function was realized using the CORDIC algorithm in which addition/subtraction and shift operations were involved and hence the performance can be improved. The throughput of the model was enhanced by the utilizing the pipelining of the design. The algorithm has been realized using vhdl in the stratix II FPGA and the algorithm was synthesized using the Quartus -11 9.1 SP2 software.
Keywords: Pipelined, Parallel,CORDIC, arcsine, arccosine, sine, cosine, FPGA, ASIC
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