Advanced VLSI Technique for Error Detection and Correction in Space Systems

Suresh TechLabs

This study introduces a novel approach to error detection and correction within Very Large-Scale Integration (VLSI) systems, specifically tailored for space applications. The core of this research is the development and implementation of a sophisticated 2-dimensional error correction code designed to significantly enhance memory reliability in the harsh conditions of outer space. Traditional error correction methods, while effective to a certain extent, fall short in addressing the complex phenomenon of burst errors—errors that occur in multiple bits simultaneously as a result of a single disruptive event, such as cosmic radiation. The proposed error correction scheme innovatively employs extended XOR operations, covering larger blocks of data, thus offering a more comprehensive solution for detecting and correcting burst errors. Moreover, the integration of Cyclic Redundancy Check (CRC) techniques further bolsters the error detection and correction capabilities of the system. Through a detailed comparison with existing methods, our study demonstrates that the proposed 2-dimensional code not only addresses the limitations of current error correction techniques but also contributes to the advancement of memory system reliability in space engineering. The implementation of this method is poised to provide better performance in environments where burst errors are prevalent, marking a significant step forward in the domain of space system design and reliability. 

 Key words: Error detection, Error correction, Cyclic Redundancy Check (CRC), XOR operations, burst errors, Space engineering, VLSI systems.  

Read More

Design and Implementation of Trigonometric Functions with High Speed CORDIC Algorithm

Suresh TechLabs

The Present work focuses on realization of the exponential and converse exponential functions by utilizing the CORDIC algorithm. The exponential function finds its application in the areas of signal processing, image processing and video processing. The realization of the exponential functions forms the bottleneck for refining the performance of the design in terms of area and delay. The range of the inputs are extended from -7 to 7. The inputs are scaled by 65536 to improve the accuracy of the result. The output values are 1 floating point values and hence they are scaled by the 65536 to get the actual values. The exponential function was realized using the CORDIC algorithm in which addition/subtraction and shift operations were involved and hence the performance can be improved. The throughput of the model was enhanced by the utilizing the pipelining of the design. The algorithm has been realized using vhdl in the stratix II FPGA and the algorithm was synthesized using the Quartus -11 9.1 SP2 software.

 Keywords: Pipelined, Parallel,CORDIC, arcsine, arccosine, sine, cosine, FPGA, ASIC

Read More

Router in Bi-Network on Chip with an Advanced FIFO Structure

Suresh TechLabs

Network on chip (NoC) becomes a promising solution for intercommunication infrastructure in System on Chip (SoC) as traditional methods exhibit severe bottlenecks at intercommunication among processor elements. However, designing of NoC is majorly complex because of lot of issues raise in terms of performance metrics such as system scalability, latency, power consumption and signal integrity. This paper discussed issues of memory unit in router and thereafter, proposing advanced memory structure. To obtain efficient data transfer, FIFO buffers are implemented in distributed RAM and virtual channels for FPGA based NoC. An advanced FIFO based memory units are proposed in NoC router and the performance is evaluated in Bi-directional NoC (Bi-NoC). The major motivation of this paper is to reduce burden of router while improving FIFO internal structure. To enhance the speed data transfer, Bi-NoC with a self-configurable intercommunication channel is proposed. The Simulations and synthesis results are proven guaranteed throughput, predictable latency, and fair network access highly provided when compared to recent works. Keywords: Network on Chip , system on chip , FIFO , FPGA.

Read More

Advanced VLSI Technique for Error Detection and Correction in Space Systems - IJISEA Journal

This study introduces a novel approach to error detection and correction within Very Large-Scale Integration (VLSI) systems, specifically tailored for space applications. The core of this research is the development and implementation of a sophisticated 2-dimensional error correction code designed to significantly enhance memory reliability in the harsh conditions of outer space. Traditional error correction methods, while effective to a certain extent, fall short in addressing the complex phenomenon of burst errors—errors that occur in multiple bits simultaneously as a result of a single disruptive event, such as cosmic radiation. The proposed error correction scheme innovatively employs extended XOR operations, covering larger blocks of data, thus offering a more comprehensive solution for detecting and correcting burst errors. Moreover, the integration of Cyclic Redundancy Check (CRC) techniques further bolsters the error detection and correction capabilities of the system. Through a detailed comparison with existing methods, our study demonstrates that the proposed 2-dimensional code not only addresses the limitations of current error correction techniques but also contributes to the advancement of memory system reliability in space engineering. The implementation of this method is poised to provide better performance in environments where burst errors are prevalent, marking a significant step forward in the domain of space system design and reliability.

 

Key words: Error detection, Error correction, Cyclic Redundancy Check (CRC), XOR operations, burst errors, Space engineering, VLSI systems. 

Read More

Coal Safety and Security System for monitoring the Environment with Driver less vehicle

The safety of coal mine is an important link in coal mine production, Gas disaster is the most harmful for the safety of coal mine production. During the process of mine development, it is very important to measure the gas, temperature and fire concentration in mines to safe the human life. Based on continuous revolution of coal mining technology, to forward this project about safety monitoring system of coal mine using Bluetooth technology. A system is designed using group of sensors which monitors the different environmental condition in underground mines and if value exceeds from threshold value, then the Miners are informed through buzzer. Another module is 16*2 LCD displays which is used to show the results of sensor condition in project. The system is flexible in the architecture of software and hardware, and can easily extend to other mine safety production fields. Keywords: Sensors, Bluetooth Technology, coal mine, underground mines

Read More

Design and Implementation of 32-bit ALU with 32 Operations for FPGA-Based RISC Architecture Applications

The project focuses on the design and the implantation of a 32-bit Arithmetic Logic Unit (ALU) capable of performing 32 different arithmetic and logic operations based on select lines. The ALU is implemented using Verilog hardware description language (HDL) and synthesized on FPGA hardware. Each operation is selected using a 5-bit control input, enabling a wide range of arithmetic and logical computations. Primary objective is to showcase the ALU’s functionality and versatility across diverse computing tasks. To optimize power consumption and hardware utilization, the design incorporates clock gating techniques and pipelining, ensuring efficient operation in resource constrained environments. Pipelining enhances throughput by breakdown operations into sequential stages, maximizing alu utilization. Through extensive simulation and synthesis, the ALU design is rigorously validated demonstrating both correctness and efficiency in operation. Vivado was utilized for a synthesis and implementation process, ensuring compatibility with FPGA hardware. The ALU is synthesized on Artix 7. FPGA platform, containing 61 cells, 135 i/o port and 1005 nets. Its design to carry out various arithmetic and logic tasks with each operation chosen using a 5-bit control input. 

https://ijisea.org/Papers/V5S1/Design%20and%20Implementation%20of%2032-bit%20ALU%20with%2032%20Operations%20for%20FPGA-Based%20RISC%20Architecture%20Applications.pdf  

Read More

Enhancing Scalability and Privacy in 5G-Enabled IoT Networks through Block chain Integration and AI Solutions - Indexed in Google Scholar : IJISEA

The proliferation of Internet of Things (IoT) devices in the digital landscape has ushered in a new era of connectivity, empowering billions of devices to communicate over the internet. However, the reliance on centralized protocols for data transfer poses significant security challenges. The emergence of 5G technology promises high-speed data transfer, yet it also underscores the need for robust security measures. Integrating Artificial Intelligence (AI) with 5G networks offers solutions to various challenges, including security concerns and the demand for autonomous systems like self-driving vehicles and virtual reality applications. Blockchain technology, known for its decentralized ledger system, presents an opportunity to address security and trust issues in IoT environments. However, integrating blockchain with IoT networks presents its own set of challenges, particularly in terms of throughput limitations. This paper addresses these challenges by proposing a solution that combines a Blockchain Distributed Network with the Raft consensus algorithm to enhance network scalability and throughput. Additionally, privacy concerns inherent in blockchain ledgers are addressed using zkLedger, a zero-knowledge based cryptographic solution. Through these innovations, this research contributes to the development of secure, scalable, and privacy-preserving 5G-enabled IoT networks.

 Key words: Blockchain, Artificial Intelligence, Internet of Things, 5G Network, Scalability, Privacy. Abbreviations: Blockchain (BC), Artificial Intelligence (AI), Internet of Things (IoT), 5G Network, Scalability (SC), Privacy (PR).

Suresh TechLabs

Read More

Indexed in - Google Scholar

Optimization of PAPR in OFDM using Orthogonal Selective Level Mapping (SLM)

Indexed in - Google Scholar

Abstract— To optimize the PAPR in conventional OFDM, Low Complexity Selective Level Mapping (SLM) is considered in this paper as it reduces PAPR significantly without loss of information. Orthogonal Frequency Division Multiplexing (OFDM) is the multicarrier modulation techniques, and it provides the provides the high spectral efficiency, low complication in implementation, less sensitivity to echoes and distortion. Due to these advantages of OFDM system is vastly used in various communication systems. But the major drawback of OFDM system is increase in peak power due to coherent addition of sub carriers. OFDM signal is the sum of many independently modulated sinusoidal waves and the amplitude is almost Rayleigh distribution. Amplitude of OFDM signal shows strong fluctuations and the resultant high Peak-to Average. Several techniques have been proposed to reduce PAPR, Low Complexity SLM can be employed in this paper to reduce PAPR in an OFDM system. In Low complexity SLM, PAPR can be reduced by multiplying the original signal with Orthogonal vector and generate statistically independent sequences which represent the same information before IFFT operation in OFDM system. The resulting independent data blocks are then forwarded into IFFT operation simultaneously and generate OFDM signal sequences.

After that compute the PAPR for all the OFDM signal sequences. Finally, the one sequence with the smallest PAPR will be selected for transmission. The proposed SLM scheme achieves similar PAPR reduction performance with much lower computational complexity compared with the conventional SLM scheme. The performance of the proposed SLM scheme is verified with various modulation schemes. The results are simulated using MATLAB.

Keywords— Selective Level Mapping (SLM), OFDM, Peak to Average Power Ratio

Read More

Published : International Journal with ISSN Number

Published : International Journal with ISSN Number

Digital Image Processing - Research Opportunities and Challenges

Interest in digital image processing methods stems from two principal application areas: improvement of pictorial information for human interpretation; and processing of image data for storage, transmission, and representation for autonomous machine perception. The objectives of this article is to define the meaning and scope of image processing, discuss the various steps and methodologies involved in a typical image processing, and applications of image processing tools and processes in the frontier areas of research.

Key Words: Image Processing, Image analysis, applications, research.

Read More