Suresh TechLabs
This paper presents an efficient FPGA based low power
pipelined 32-bit RISC processor with Floating Point Unit. RISC is a design philosophy where it reduces the complexity of the
instruction set, which will reduce the amount of space, time, cost, power and
heat etc.,. This processor is developed
especially for Arithmetic operations of both
fixed and floating point as it is implemented using dynamic branch
prediction. This will increase flow in instruction
pipeline and high effective performance. In RTL coding one can reduce the
dynamic power by using clock gating technique. In this paper also implement
Double Precision floating point arithmetic operations like addition,
subtraction, multiplication and division. This architecture has become
indispensable and increasingly important in
many applications like signal processing, graphics and medical by using
floating point operations. The necessary code is
written in the hardware
description language Verilog HDL. Quartus II 10.1 suite is used for software development, Modelsim is used for simulations and the design is implemented on Altera's Cyclone
DElIFPGA.