Advanced VLSI Technique for Error Detection and Correction in Space Systems

Suresh TechLabs

This study introduces a novel approach to error detection and correction within Very Large-Scale Integration (VLSI) systems, specifically tailored for space applications. The core of this research is the development and implementation of a sophisticated 2-dimensional error correction code designed to significantly enhance memory reliability in the harsh conditions of outer space. Traditional error correction methods, while effective to a certain extent, fall short in addressing the complex phenomenon of burst errors—errors that occur in multiple bits simultaneously as a result of a single disruptive event, such as cosmic radiation. The proposed error correction scheme innovatively employs extended XOR operations, covering larger blocks of data, thus offering a more comprehensive solution for detecting and correcting burst errors. Moreover, the integration of Cyclic Redundancy Check (CRC) techniques further bolsters the error detection and correction capabilities of the system. Through a detailed comparison with existing methods, our study demonstrates that the proposed 2-dimensional code not only addresses the limitations of current error correction techniques but also contributes to the advancement of memory system reliability in space engineering. The implementation of this method is poised to provide better performance in environments where burst errors are prevalent, marking a significant step forward in the domain of space system design and reliability. 

 Key words: Error detection, Error correction, Cyclic Redundancy Check (CRC), XOR operations, burst errors, Space engineering, VLSI systems.  

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Design and Implementation of Trigonometric Functions with High Speed CORDIC Algorithm

Suresh TechLabs

The Present work focuses on realization of the exponential and converse exponential functions by utilizing the CORDIC algorithm. The exponential function finds its application in the areas of signal processing, image processing and video processing. The realization of the exponential functions forms the bottleneck for refining the performance of the design in terms of area and delay. The range of the inputs are extended from -7 to 7. The inputs are scaled by 65536 to improve the accuracy of the result. The output values are 1 floating point values and hence they are scaled by the 65536 to get the actual values. The exponential function was realized using the CORDIC algorithm in which addition/subtraction and shift operations were involved and hence the performance can be improved. The throughput of the model was enhanced by the utilizing the pipelining of the design. The algorithm has been realized using vhdl in the stratix II FPGA and the algorithm was synthesized using the Quartus -11 9.1 SP2 software.

 Keywords: Pipelined, Parallel,CORDIC, arcsine, arccosine, sine, cosine, FPGA, ASIC

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Router in Bi-Network on Chip with an Advanced FIFO Structure

Suresh TechLabs

Network on chip (NoC) becomes a promising solution for intercommunication infrastructure in System on Chip (SoC) as traditional methods exhibit severe bottlenecks at intercommunication among processor elements. However, designing of NoC is majorly complex because of lot of issues raise in terms of performance metrics such as system scalability, latency, power consumption and signal integrity. This paper discussed issues of memory unit in router and thereafter, proposing advanced memory structure. To obtain efficient data transfer, FIFO buffers are implemented in distributed RAM and virtual channels for FPGA based NoC. An advanced FIFO based memory units are proposed in NoC router and the performance is evaluated in Bi-directional NoC (Bi-NoC). The major motivation of this paper is to reduce burden of router while improving FIFO internal structure. To enhance the speed data transfer, Bi-NoC with a self-configurable intercommunication channel is proposed. The Simulations and synthesis results are proven guaranteed throughput, predictable latency, and fair network access highly provided when compared to recent works. Keywords: Network on Chip , system on chip , FIFO , FPGA.

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Published UGC CARE I Journal

Published UGC CARE I Journal

Printed Dipole-Loop Antenna with High Gain for RF Energy Harvesting Applications

Abstract—In this paper, a compact dual-band antenna for RF energy harvesting applications is presented. The basic antenna structure is formed using a combination between a dipole and a loop antenna to operate at 900 MHz and 1600 MHz, respectively. To enable the antenna to resonate at a dual- band within a compact substrate, two L-shaped vertical arms as a dipole connected with a trapezoidal slot loop. A meandered transmission line is connected to the coplanar slot line to act as a stub to match the input impedance of the dipole and the loop. On the back of the antenna, a reflector is positioned to enhance the forward to back ratio and provide a unidirectional radiation pattern. The antenna has a compact size 0.149λo 0.23λo (with respect to the wavelength at the lowest operating frequency),making it comparatively smaller than similar designs. It has a measured fractional bandwidth of 11% at 0.970 GHz at the lower band and 52.9% at the upper band from 1.5 to 2.58 GHz. The antenna performance has a peak gain of 6.5 dB. To prove the antenna normal operation, a prototype is fabricated, tested and the measurements are compared against the simulation results. This antenna is intended for the RF wireless energy harvesting applications.

Suresh Tech Labs 

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Published - UGC CARE II Journal

Published - UGC CARE II Journal

High Speed Low Power Pre-Charge CAM Design  using Hybrid self-control

Abstract :  In this paper, we present a novel content addressable memory (CAM) is discussed. Although it uses more power, ontent-addressable memory (CAM) is a popular piece of hardware for high-speed lookup searches. Traditional NOR and NAND match-line (ML) architectures experience charge and short circuit path sharing during pre-charge, respectively. The pre-charge-free CAM that was recently proposed has a high search cost. delay and excessive power consumption of the subsequently proposed elf-controlled pre-charge-free CAM. In order to decrease search delay and power consumption, the hybrid self-controlled pre- harge-free (HSCPF) CAM architecture presented in this study employs a unique charge control circuitry. Both the present and planned CAM ML designs were created using the CMOS 45nm technology node and a 1 V supply voltage. When compared to, simulation results demonstrate that the suggested HSCPF CAM-type ML design effectively reduces power consumption and search latency. 

 Keywords: Content Memory Address, hybrid model, Precharge phase.

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